1. Field of the Invention
The present invention generally relates to self-resetting complementary metal oxide semiconductor (CMOS) circuits manufactured as integrated circuit (IC) chips and, more specifically, to a reset generating circuit to reset the self-resetting CMOS (SRCMOS) circuits during regular and long clock cycles.
2. Description of the Prior Art
The basic concept of an SRCMOS circuit is to provide a high speed timed data path. In the beginning of a cycle, a RESET signal makes a transition from high to low. This will charge a node of the circuit to the supply voltage. The RESET pulse is approximately 700 picoseconds wide. After a certain time delay, a data signal on an input terminal will go from low to high. This action will discharge the precharged node to ground, causing the output signal at an output terminal to go high. In the beginning of every cycle or, in certain cases, at the end of each cycle, the RESET signal will pulse.
The RESET generation circuit for the SRCMOS circuit creates two problems. First, under certain conditions, the RESET signal will oscillate. Second, a very wide clock pulse width used in the circuit can cause a collision current phenomena.